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ads822 ads825 10-bit, 40mhz sampling analog-to-digital converters features l high snr: 60db l high sfdr: 72dbfs l low power: 190mw l internal/external reference option l single-ended or fully differential analog input l programmable input range l low dnl: 0.5lsb l single +5v supply operation l +3v or +5v logic i/o compatible (ads825) l power down: 20mw l ssop-28 package applications l medical imaging l test equipment l computer scanners l communications l video digitizing description the ads822 and ads825 are pipeline, cmos analog-to- digital converters (adc) that operate from a single +5v power supply. these converters provide excellent performance with a single-ended input and can be operated with a differential input for added spurious performance. these high-performance con- verters include a 10-bit quantizer, high-bandwidth track-and- hold, and a high-accuracy internal reference. they also allow for the user to disable the internal reference and utilize external references. this external reference option provides excellent gain and offset matching when used in multi-channel applications or in applications where full-scale range adjustment is required. the ads822 and ads825 employ digital error correction tech- niques to provide excellent differential linearity for demanding imaging applications. its low distortion and high snr give the extra margin needed for medical imaging, communications, video, and test instrumentation. the ads822 and ads825 offer power dissipation of 190mw and also provide a power-down mode, thus reducing power dissipation to only 20mw. the ads825 is +3v or +5v logic i/o compatible. the ads822 and ads825 are specified at a maximum sampling frequency of 40mhz and a single-ended input range of 1.5v to 3.5v. the ads822 and ads825 are available in a ssop-28 package and are pin-for-pin compatible with the 10-bit, 60mhz ads823 and ads826, and the 10-bit, 70mhz ads824, provid- ing an upgrade path to higher sampling frequencies. tm ? 1997 burr-brown corporation pds-1385f printed in u.s.a. july, 2000 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 for most current data sheet and other product information, visit www.burr-brown.com 10-bit pipelined a/d core internal reference optional external reference timing circuitry error correction logic 3-state outputs t/h clk vdrv ads822 ads825 +v s oe pd int/ext d0 d9 in v in in cm ads822 ads825
2 ads822, ads825 specifications at t a = full specified temperature range, v s = +5v, single-ended input range = 1.5v to 3.5v, and sampling rate = 40mhz, external reference, unless otherwise noted. cmos-compatible rising edge of convert clock cmos-compatible straight offset binary cmos-compatible straight offset binary ads822e ADS825E (1) parameter conditions min typ max min typ max units resolution 10 guaranteed 10 guaranteed bits specified temperature range ambient air C40 to +85 C40 to +85 c analog input standard single-ended input range 2vp-p 1.5 3.5 [[ v optional single-ended input range 1vp-p 2 3 [[ v common-mode range 2.5 [ v optional differential input range 2vp-p 2 3 [[ v analog input bias current 1 [ m a input impedance 1.25 || 5 [ m w || pf track-mode input bandwidth C3dbfs input 300 [ mhz conversion characteristics sample rate 10k 40m [[ samples/s data latency 5 [ clk cyc dynamic characteristics differential linearity error (largest code error) f = 1mhz 0.25 1.0 [[ lsb f = 10mhz 0.5 [ lsb no missing codes guaranteed guaranteed integral nonlinearity error, f = 1mhz 0.5 2.0 [[ lsbs spurious free dynamic range (2) referred to full scale f = 1mhz 72 71 dbfs (3) f = 10mhz 63 66 60 65 dbfs two-tone intermodulation distortion (4) f = 9.5mhz and 9.9mhz (C7db each tone) C67 [ dbc signal-to-noise ratio (snr) referred to full scale f = 1mhz 60 [ db f = 10mhz 57 60 [[ db signal-to-(noise + distortion) (sinad) referred to full scale f = 1mhz 59 [ db f = 10mhz 56 58 [[ db effective number of bits (5) , f = 1mhz 9.5 [ bits output noise input tied to common-mode 0.2 [ lsbs rms aperture delay time 3 [ ns aperture jitter 1.2 [ ps rms overvoltage recovery time 2 [ ns full-scale step acquisition time 5 [ ns digital inputs logic family convert command start conversion high level input current (6) (v in = 5v dd ) 100 [ m a low level input current (v in = 0v) 10 [ m a high level input voltage +3.5 +2.0 v low level input voltage +1.0 +0.8 v input capacitance 5 [ pf digital outputs logic family logic coding low output voltage (i ol = 50 m a to 1.6ma) vdrv = 5v +0.1 [ v high output voltage, (i oh = 50 m a to 0.5ma) +4.9 [ v low output voltage, (i ol = 50 m a to 1.6ma) vdrv = 3v +0.1 [ v high output voltage, (i oh = 50 m a to 0.5ma) +2.8 [ v 3-state enable time oe = h to l 2 40 [[ ns 3-state disable time oe = l to h 2 10 [[ ns output capacitance 5 [ pf accuracy (internal reference, 2vp-p, unless otherwise noted) zero error (referred to Cfs) at 25 c 1.0 3.0 [[ % fs zero error drift (referred to Cfs) 5 [ ppm/ c midscale offset error at 25 c 0.29 % fs gain error (7) at 25 c 1.5 3.5 [[ % fs gain error drift (7) 38 [ ppm/ c gain error (8) at 25 c 0.75 2.5 [[ % fs gain error drift (8) 25 [ ppm/ c power supply rejection of gain d v s = 5% 70 [ db reft tolerance deviation from ideal 3.5v 10 25 [[ mv refb tolerance (9) deviation from ideal 1.5v 10 25 [[ mv external reft voltage range refb + 0.8 3.5 v s C 1.25 [[[ v external refb voltage range 1.25 1.5 reft C 0.8 [[[ v reference input resistance reft to refb 1.6 [ k w ttl, +3v/+5v cmos-compatible rising edge of convert clock
3 ads822, ads825 specifications (cont.) at t a = full specified temperature range, v s = +5v, single-ended input range = 1.5v to 3.5v, and sampling rate = 40mhz, external reference, unless otherwise noted. pin designator description 1 gnd ground 2 bit 1 data bit 1 (d9) (msb) 3 bit 2 data bit 2 (d8) 4 bit 3 data bit 3 (d7) 5 bit 4 data bit 4 (d6) 6 bit 5 data bit 5 (d5) 7 bit 6 data bit 6 (d4) 8 bit 7 data bit 7 (d3) 9 bit 8 data bit 8 (d2) 10 bit 9 data bit 9 (d1) 11 bit 10 data bit 10 (d0) (lsb) 12 oe output enable. hi = high impedance state lo = normal operation (internal pull-down resistor) 13 pd power down. hi = enable; lo = disable 14 clk convert clock input 15 +v s +5v supply 16 gnd ground 17 rsel input range select. hi = 2v; lo = 1v 18 int/ext reference select. hi = external, lo = internal 19 refb bottom reference 20 byb bottom ladder bypass 21 byt top ladder bypass 22 reft top reference 23 cm common-mode voltage output 24 in complementary input (C) 25 in analog input (+) 26 gnd analog ground 27 +v s +5v supply 28 vdrv output logic driver supply voltage pin descriptions top view ssop pin configuration power supply requirements supply voltage: +v s operating +4.75 +5.0 +5.25 [[[ v supply current: +i s operating (external reference) 40 [ ma power dissipation: vdrv = 5v external reference 200 230 [[ mw vdrv = 3v external reference 190 [ mw vdrv = 5v internal reference 250 [ mw vdrv = 3v internal reference 240 [ mw power down operating 20 [ mw thermal resistance, q ja 28-lead ssop 89 [ c/w [ indicates the same specifications as the ads822e. notes: (1) ADS825E accepts a +3v clock input. (2) spurious free dynamic range refers to the magnitude of the largest harmonic. (3) dbfs means db relative to full scale. (4) two-tone intermodulation distortion is referred to the largest fundamental tone. this number will be 6db higher if it is referred to the magnitude of th e two-tone fundamental envelope. (5) effective number of bits (enob) is defined by (sinad C 1.76)/6.02. (6) a 50k w pull-down resistor is inserted internally on oe pin. (7) includes internal reference. (8) excludes internal reference. (9) gua ranteed by design. ads822e ADS825E (1) parameter conditions min typ max min typ max units gnd bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 (lsb) oe pd clk vdrv +v s gnd in in cm reft byt byb refb int/ext rsel gnd +v s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ads822 ads825
4 ads822, ads825 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifica tions are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. timing diagram 5 clock cycles data invalid t d t l t h t conv n? n? n? n? n? n n+1 n+2 data out clock analog in n t 2 n+1 n+2 n+3 n+4 n+5 n+6 n+7 t 1 symbol description min typ max units t conv convert clock period 25 100 m sns t l clock pulse low 11.5 12.5 ns t h clock pulse high 11.5 12.5 ns t d aperture delay 3 ns t 1 data hold time, c l = 0pf 3.9 ns t 2 new data delay time, c l = 15pf max 12 ns electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. +v s ....................................................................................................... +6v analog input ............................................................. C0.3v to (+v s + 0.3v) logic input ............................................................... C0.3v to (+v s + 0.3v) case temperature ......................................................................... +100 c junction temperature .................................................................... +150 c storage temperature ..................................................................... +150 c absolute maximum ratings package specified drawing temperature package ordering transport product package number range marking number (1) media ads822e ssop-28 324 C40 c to +85 c ads822e ads822e rails " " " " " ads822e/1k tape and reel ADS825E ssop-28 324 C40 c to +85 c ADS825E ADS825E rails " " " " " ADS825E/1k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /1k indicates 1000 dev ices per reel). ordering 1000 pieces of ads822e/1k will get a single 1000-piece tape and reel. package/ordering information product demo board ads822e dem-ads822e demo board ordering information
5 ads822, ads825 spectral performance frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f in = 10mhz spectral performance (single-ended, 1vp-p) frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f in = 20mhz snr = 57dbfs sfdr = 70dbfs spectral performance (single-ended, 1vp-p) frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f in = 10mhz snr = 57dbfs sfdr = 71dbfs spectral performance (differential input, 1vp-p) frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f in = 10mhz snr = 58dbfs sfdr = 74dbfs spectral performance frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f in = 1mhz undersampling (differential input, 2vp-p) frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f s = 40mhz f in = 45mhz snr = 60dbfs sfdr = 74dbfs typical performance curves at t a = full specified temperature range, v s = +5v, single-ended input range = 1.5v to 3.5v, and sampling rate = 40mhz, external reference, unless otherwise noted.
6 ads822, ads825 undersampling (differential input, 2vp-p) frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f s = 40mhz f in = 75mhz snr = 59dbfs sfdr = 66dbfs two-tone intermodulation distortion frequency (mhz) magnitude (db) 0 ?0 ?0 ?0 ?0 ?00 0 5 10 15 20 f 1 = 9.5mhz at ?dbfs f 2 = 9.9mhz at ?dbfs imd (3) = ?7db integral linearity error output code ile (lsb) 2.0 1.0 0 ?.0 ?.0 0 256 512 768 1024 differential linearity error output code dle (lsb) 1.0 0.5 0 ?.5 ?.0 0 20 40 60 80 1024 f in = 10mhz differential linearity error output code dle (lsb) 1.0 0.5 0 ?.5 ?.0 0 20 40 60 80 1024 f in = 1mhz typical performance curves (cont.) at t a = full specified temperature range, v s = +5v, single-ended input range = 1.5v to 3.5v, and sampling rate = 40mhz, external reference, unless otherwise noted. swept power sfdr input amplitude (dbfs) 100 80 60 40 20 0 ?0 ?0 ?0 ?0 ?0 ?0 0 sfdr (dbfs, dbc) dbc dbfs
7 ads822, ads825 typical performance curves (cont.) at t a = full specified temperature range, v s = +5v, single-ended input range = 1.5v to 3.5v, and sampling rate = 40mhz, external reference, unless otherwise noted. 75 70 65 60 55 dynamic performance vs temperature sfdr, snr (dbfs) ?0 ?5 0 25 50 75 100 temperature (?) sfdr (f in = 10mhz) snr (f in = 10mhz) snr (f in = 20mhz) sfdr (f in = 20mhz) 60 59 58 57 signal-to-(noise + distortion) vs temperature sinad (dbfs) ?0 ?5 0 25 50 75 100 temperature (?) f in = 1mhz f in = 20mhz f in = 10mhz .60 .50 .40 .30 differential linearity error vs temperature dle (lsb) ?0 ?5 0 25 50 75 100 temperature (?) f in = 10mhz f in = 20mhz 800k 600k 400k 200k 0 output noise (dc input) counts n-2 n-1 n n+1 n+2 code dynamic performance vs input frequency frequency (mhz) 75 70 65 60 55 50 0.1 1 10 100 sfdr, snr (dbfs) snr sfdr power dissipation vs temperature temperature (?) 205 200 195 190 ?0 0 25 ?5 50 75 100 power (mw)
8 ads822, ads825 application information theory of operation the ads822 and ads825 are high-speed cmos adcs which employ a pipelined converter architecture consisting of 9 internal stages. each stage feeds its data into the digital error correction logic ensuring excellent differential linear- ity and no missing codes at the 10-bit level. the output data becomes valid on the rising clock edge (see timing dia- gram). the pipeline architecture results in a data latency of 5 clock cycles. the analog inputs of the ads822 and ads825 are differen- tial track-and-hold (see figure 1). the differential topology, along with tightly matched capacitors, produce a high level of ac performance while sampling at very high rates. the ads822 and ads825 allow their analog inputs to be driven either single-ended or differentially. the typical con- figuration for the ads822 and ads825 is the single-ended mode in which the input track-and-hold performs a single- ended-to-differential conversion of the analog input signal. both inputs (in, in) require external biasing using a com- mon-mode voltage that is typically at the mid-supply level (+v s /2). the following application discussion focuses on the single- ended configuration. typically, its implementation is easier to achieve and the rated specifications for the ads822 and ads825 are characterized using the single-ended mode of operation. driving the analog input the ads822 and ads825 achieve excellent ac performance either in the single-ended or differential mode of operation. figure 1. simplified circuit of input track-and-hold with timing diagram. the selection for the optimum interface configuration will depend on the individual application requirements and sys- tem structure. for example, communications applications often process a band of frequencies that do not include dc, whereas in imaging applications, the previously restored dc level must be maintained correctly up to the adc. features on the ads822 and ads825, such as the input range select (rsel pin) or the option for an external reference, provide the needed flexibility to accommodate a wide range of applications. in any case, the ads822 and ads825 should be configured such that the application objectives are met while observing the headroom requirements of the driving amplifier in order to yield the best overall performance. input configurations ac-coupled, single-supply interface figure 2 shows the typical circuit for an ac-coupled analog input configuration of the ads822 and ads825 while all components are powered from a single +5v supply. with the rsel pin connected high, the full-scale input range is set to 2vp-p. in this configuration, the top and bottom references (reft, refb) provide an output voltage of +3.5v and +1.5v, respectively. two resistors ( 2x 1.62k w ) are used to create a common-mode voltage (v cm ) of ap- proximately +2.5v to bias the inputs of the driving amplifier a1. using the opa680 on a single +5v supply, its ideal common-mode point is at +2.5v which coincides with the recommended common-mode input level for the ads822 and ads825. this obviates the need of a coupling capacitor between the amplifier and the converter. even though the opa680 has an ac gain of +2, the dc gain is only +1 due to the blocking capacitor at resistor r g . the addition of a small series resistor (r s ) between the output of the op amp and the input of the ads822 and ads825 will be beneficial in almost all interface configura- tions. this will decouple the op amps output from the capacitive load and avoid gain peaking, which can result in increased noise. for best spurious and distortion perfor- mance, the resistor value should be kept below 100 w . furthermore, the series resistor in combination with the 10pf capacitor establishes a passive low-pass filter limiting the bandwidth for the wideband noise, thus helping improve the snr performance. ac-coupled, dual supply interface the circuit provided in figure 3 shows typical connections for the analog input in case the selected amplifier operates on dual supplies. this might be necessary to take full advantage of very low distortion operational amplifiers, like the opa642. the advantage is that the driving amplifier can be operated with a ground referenced bipolar signal swing. this will keep the distortion performance at its lowest since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be main- tained. by capacitively coupling the single-ended signal to the input of the ads822 and ads825, its common-mode requirements can easily be satisfied with two resistors con- nected between the top and bottom reference. f 1 f 1 f 2 f 1 f 1 f 1 f 1 f 1 f 2 f 1 f 2 f 1 f 2 in in out out op amp bias v cm op amp bias v cm c h c i c i c h input clock (50%) internal non-overlapping clock
9 ads822, ads825 figure 2. ac-coupled input configuration for a 2vp-p full-scale range and a common-mode voltage, v cm , at +2.5v derived from the internal top (reft) and bottom reference (refb). figure 3. ac-coupling the dual supply amplifier opa642 to the ads822 for a 2vp-p full-scale input range. for applications requiring the driving amplifier to provide a signal amplification, with a gain 3 5, consider using decom- pensated voltage-feedback op amps, like the opa643, or current-feedback op amps like the opa681 and opa658. dc-coupled with level shift several applications may require that the bandwidth of the signal path include dc, in which case, the signal has to be dc-coupled to the adc. in order to accomplish this, the interface circuit has to provide a dc level shift to the analog input signal. the circuit shown in figure 4 employs a dual op amp, a1, to drive the input of the ads822 and ads825, and level shifts the signal to be compatible with the selected input range. with the rsel pin tied to the supply and the int/ext pin to ground, the ads822 and ads825 are configured for a 2vp-p input range and use the internal references. the complementary input (in) may be appropri- ately biased using the +2.5v common-mode voltage avail- able at the cm pin. one half of amplifier a1 buffers the refb pin and drives the voltage divider r 1 , r 2 . due to the op amps noise gain of +2v/v, assuming r f = r in , the common-mode voltage (v cm ) has to be re-scaled to +1.25v. this results in the correct dc level of +2.5v for the signal input (in). any dc voltage differences between the in and in inputs of the ads822 and ads825 effectively produces an offset, which can be corrected for by adjusting the resistor values of the divider, r 1 and r 2 . the selection criteria for a suitable op amp should include the supply voltage, input bias current, output voltage swing, distortion, and noise specifi- cation. note that in this example, the overall signal phase is inverted. to re-establish the original signal polarity, it is always possible to interchange the in and in connections. +v in 0v ? in opa680 v in r f 402 w 1.62k w r g 402 w ads822 ads825 r s 50 w 10pf 0.1 f in in cm int/ext gnd reft +3.5v 1.62k w 50 w v cm +2.5v refb +1.5v 0.1 m f 0.1 f rsel +v s +5v +5v opa642 v in r f 402 w 1.62k w r g 402 w ads822 ads825 r s 24.9 w 1.62k w 100pf 0.1 f 0.1 m f in in cm refb +1.5v int/ext gnd reft +3.5v rsel +v s +5v +5v ?v
10 ads822, ads825 figure 4. dc-coupled interface circuit with dual current-feedback amplifier opa2681. figure 5. transformer coupled input. figure 6. equivalent reference circuit with recommended reference bypassing. single-ended-to-differential configuration (transformer coupled) if the application requires a signal conversion from a single- ended source to feed the ads822 and ads825 differen- tially, a rf transformer might be a good solution. the selected transformer must have a center tap in order to apply the common-mode dc voltage necessary to bias the con- verter inputs. ac-grounding the center tap will generate the differential signal swing across the secondary winding. con- sider a step-up transformer to take advantage of a signal amplification without the introduction of another noise source. furthermore, the reduced signal swing from the source may lead to an improved distortion performance. the differential input configuration may provide a notice- able advantage of achieving good sfdr performance over a wide range of input frequencies. in this mode, both inputs of the ads822 and ads825 see matched impedances, and the differential signal swing can be reduced to half of the swing required for single-ended drive. figure 5 shows the schematic for the suggested transformer-coupled interface circuit. the component values of the r-c low-pass may be optimized depending on the desired roll-off frequency. the resistor across the secondary side (r t ) should be calculated using the equation r t = n 2 ? r g to match the source impedance (r g ) for good power transfer and voltage standing wave ratio (vswr). reference operation figure 6 depicts the simplified model of the internal refer- ence circuit. the internal blocks are the bandgap voltage reference, the drivers for the top and bottom reference, and 2vp-p note: r f = r in , g = ? v in r 2 200 w r 1 1k w ads822 ads825 r s 50 w 10pf 0.1 f in in cm (+2.5) int/ext r f 499 w r in 499 w v cm = +1.25v refb (+1.5v) reft (+3.5v) 1/2 opa2681 1/2 opa2681 r f 1k w 50 w 0.1 f 0.1 f rsel +v s +5v +5v v in in in cm 22 w 22 w 47pf r t 47pf + 10 f 0.1 f int/ext rsel +5v ads822 ads825 1:n 0.1 f r g ads822 reft byt cm byb refb bandgap reference and logic v ref 400 w 400 w 400 w 400 w +1 +1 +v s 50k w 50k w int/ext rsel bypass capacitors: 0.1 f || 2.2 f each (optionally, 2.2 f tantalum capacitors maybe added to byt and byb pins for the best results).
11 ads822, ads825 the resistive reference ladder. the bandgap reference circuit includes logic functions that allows setting the analog input swing of the ads822 and ads825 to either a 1vp-p or 2vp-p full-scale range simply by tying the rsel pin to a low or high potential, respectively. while operating the ads822 in the external reference mode, the buffer amplifi- ers for the reft and refb are disconnected from the reference ladder. as shown, the ads822 and ads825 have internal 50k w pull-up resistors at the range select pin (rsel) and refer- ence select pin (int/ext). leaving these pins open config- ures the ads822 and ads825 for a 2vp-p input range and external reference operation. setting the ads822 and ads825 up for internal reference mode requires bringing the int/ext pin low. the reference buffers can be utilized to supply up to 1ma (sink and source) to external circuitry. the resistor ladders of the ads822 and ads825 are divided into several seg- ments and have two additional nodes, byt and byb, which are brought out for external bypassing only (see figure 6). to ensure proper operation with any reference configura- tions, it is necessary to provide solid bypassing at all refer- ence pins in order to keep the clock feedthrough to a minimum. all bypassing capacitors should be located as close to their respective pins as possible. the common-mode voltage available at the cm pin may be used as a bias voltage to provide the appropriate offset for the driving circuitry. however, care must be taken not to appreciably load this node, which is not buffered and has a high impedance. an alternative way of generating a com- mon-mode voltage is given in figure 7. here, two external precision resistors (tolerance 1% or better) are located between the top and bottom reference pins. the common- mode voltage, cmv, will appear at the midpoint. external reference operation for even more design flexibility, the internal reference can be disabled and an external reference voltage be used. the utilization of an external reference may be considered for applications requiring higher accuracy, improved tempera- ture performance, or a wide adjustment range of the converters full-scale range. especially in multichannel applications, the use of a common external reference has the benefit of obtaining better matching of the full-scale range between converters. the external references can vary as long as the value of the external top reference reft ext stays within the range of (v s C 1.25v) and (refb + 0.8v), and the external bottom reference refb ext stays within 1.25v and (reft C 0.8v) (see figure 8). digital inputs and outputs clock input requirements clock jitter is critical to the snr performance of high-speed, high-resolution adcs. clock jitter leads to aperture jitter (t a ), which adds noise to the signal being converted. the ads822 and ads825 samples the input signal on the rising edge of the clk input. therefore, this edge should have the lowest possible jitter. the jitter noise contribution to total snr is figure 8. configuration example for external reference operation. figure 7. alternative circuit to generate cm voltage. reft +3.5v ads822 ads825 cmv +2.5v refb +1.5v r 1 1.6k w r 2 1.6k w 0.1 f 0.1 f ads822 ads825 in in int/ext reft byt gnd byb refb 4 x 0.1 f external top reference reft = refb +0.8v to +3.75v +vs ba rsel gnd +5v external bottom reference refb = reft ?.8v to +1.25v v in a - short for 1vp-p input range b - short for 2vp-p input range (default) cmv +2.5v dc
12 ads822, ads825 given by the following equation. if this value is near your system requirements, input clock jitter must be reduced. where: ? in is input signal frequency t a is rms clock jitter particularly in undersampling applications, special consider- ation should be given to clock jitter. the clock input should be treated as an analog input in order to achieve the highest level of performance. any overshoot or undershoot of the clock signal may cause degradation of the performance. when digitizing at high sampling rates, the clock should have 50% duty cycle (t h = t l ), along with fast rise and fall times of 2ns or less. the clock input of the ads825 can be driven with either 3v or 5v logic levels. using low-voltage logic (3v) may lead to improved ac performance of the converter. digital outputs the output data format of the ads822 and ads825 are in positive straight offset binary code (see tables i and ii). this format can easily be converted into the binary twos complement code by inverting the msb. it is recommended to keep the capacitive loading on the data lines as low as possible ( 15pf). higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. those high current surges can feed back to the analog portion of the ads822 and ads825 and affect the performance. if necessary, external buffers or latches close to the converters output pins may be used to minimize the capacitive loading. they also provide the added benefit of isolating the ads822 and ads825 from any digital noise activities on the bus coupling back high frequency noise. +v s 27 26 gnd ads822 ads825 + 0.1 f 0.1 f +v s 15 16 gnd 10 f +5v vdrv 28 0.1 f +3/+5v figure 9. recommended bypassing for the supply pins. digital output driver (vdrv) the ads822 features a dedicated supply pin for the output logic drivers, vdrv, which is not internally connected to the other supply pins. setting the voltage at vdrv to +5v or +3v, the ads822 and ads825 produce corresponding logic levels and can directly interface to the selected logic family. the output stages are designed to supply sufficient current to drive a variety of logic families. however, it is recommended to use the ads822 and ads825 with +3v logic supply. this will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the ac- performance of the converter. in some applications, it might be advantageous to decouple the vdrv pin with additional capacitors or a pi-filter. grounding and decoupling proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. multilayer pc boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. the ads822 and ads825 should be treated as analog components. whenever possible, the supply pins should be powered by the analog supply. this will ensure the most consistent results since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achiev- able performance. all ground connections on the ads822 and ads825 are internally joined together obviating the design of split ground planes. the ground pins (1, 16, 26) should directly connect to an analog ground plane which covers the pc board area around the converter. while designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. due to their high sampling rates, the ads822 and ads825 generate high frequency current transients, and noise (clock feedthrough) that are fed back into the supply and reference lines. this requires that all supply and reference pins are sufficiently bypassed. figure 9 shows the recommended decoupling scheme for the ads822 and ads825. in most cases, 0.1 m f ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. their effec- tiveness largely depends on the proximity to the individual supply pin. therefore, they should be located as close to the supply pins as possible. in addition, a larger bipolar capaci- tor (1 m f to 22 m f) should be placed on the pc board in proximity of the converter circuit. +fs C1lsb (in = +3v, in = +2v) 11 1111 1111 +1/2 full scale 11 0000 0000 bipolar zero (in = in = cmv) 10 0000 0000 C1/2 full scale 01 0000 0000 Cfs (in = +2v, in = +3v) 00 0000 0000 straight offset binary differential input (sob) table ii. coding table for differential input configuration and 2vp-p full-scale range. +fs C1lsb (in = reft) 11 1111 1111 +1/2 full scale 11 0000 0000 bipolar zero (in = cmv) 10 0000 0000 C1/2 full scale 01 0000 0000 Cfs (in = refb) 00 0000 0000 single-ended input straight offset binary (in = cmv) (sob) table i. coding table for single-ended input configura- tion with in tied to the common-mode voltage (cmv). jitter snr t rms signal to rms noise in a = | 20 1 2 log p

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